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1 1 2 3 4 8 7 6 5 cs sk di do vcc dc org gnd 1 2 3 4 8 7 6 5 cs sk di do vcc dc org gnd 1 2 3 4 8 7 6 5 cs sk di do vcc dc org gnd 8-lead pdip 8-lead soic 8-lead tssop features ? medium-voltage and standard-voltage operation ? 2.7 (v cc = 2.7v to 5.5v) user-selectable internal organization ? 1k: 128 x 8 or 64 x 16 three-wire serial interface 2 mhz clock rate (5v) self-timed write cycle (10 ms max) high reliability ? endurance: 1 million write cycles ? data retention: 100 years 8-lead pdip, 8-lead tssop an d 8-lead jedec soic packages description the at9 3 c46 provides 1024 bits of serial electrically erasable programmable read only memory (eeprom) organized as 64 words of 16 bits each, when the org pin is connected to vcc and 12 8 words of 8 bits each when it is tied to ground. the device is optimized for use in many automotive applications where low power and low voltage operations are essential. the at9 3 c46 is available in space-saving 8 -lead pdip, 8 - lead t ss op and 8 -lead jedec s oic packages. the at9 3 c46 is enabled through the chip s elect pin (c s ), and accessed via a 3 -wire serial interfac e consisting of data input (di), data output (do), and s hift clock ( s k). upon receiving a read instruction at di, the address is decoded and the data is clocked out serially on the data output pin do. the write cycle is completely self-timed and no separate erase cycle is required before write. the write cycle is onl y enabled when it is in the erase/write enable state. when c s is brought ?high? following the initiation of a write cycle, the do pin outputs the ready/busy status. table 1. pin configuration pin name function c s chip s elect s k s erial data clock di s erial data input do s erial data output gnd ground vcc power s upply org internal organization three-wire serial automotive eeproms 1k (128 x 8 or 64 x 16) at93c46 rev. 5125a? s eepr? 8 /05
2 at93c46 5125a? s eepr? 8 /05 figure 1. block diagram note: when the org pin is connected to vcc, the ?x 16? org anization is selected. when it is connected to ground, the ?x 8 ? organiza- tion is selected. if the org pin is left unconnected and the applic ation does not load the input beyond the capability of the internal 1 meg ohm pullup, then the ?x 16? organization is selected. for the at9 3 c46, if ?x 16? organization is the mode of choice and pin 6 (org) is left unconnected, atmel recommends using the at9 3 c46a device. for more details, see the at9 3 c46a datasheet. absolute maximum ratings* operating temperature ......................................? 55 c to +125 c *notice: s tresses beyond those listed under ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions beyond those indicated in the operational sec- tions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability s torage temperature .........................................? 65 c to +150 c voltage on any pin with respect to ground ........................................ ? 1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma
3 at93c46 5125a? s eepr? 8 /05 note: 1. this parameter is characterized and is not 100% tested. note: 1. v il min and v ih max are reference only and are not tested. table 2. pin capacitance (1) applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +5.0v (unless otherwise noted) symbol test conditions max units conditions c out output capacitance (do) 5 pf v out = 0v c in input capacitance (c s , s k, di) 5 pf v in = 0v table 3. dc characteristics applicable over recommended operating range from: t a = ? 40 c to +125 c, v cc = +2.7v to +5.5v (unless otherwise noted) symbol parameter test condition min typ max unit v cc1 s upply voltage 2.7 5.5 v v cc2 s upply voltage 4.5 5.5 v i cc s upply current v cc = 5.0v read at 1.0 mhz 0.5 2.0 ma write at 1.0 mhz 0.5 2.0 ma i s b1 s tandby current v cc = 2.7v c s = 0v 6.0 10.0 a i s b2 s tandby current v cc = 5.0v c s = 0v 17 3 0a i il input leakage v in = 0v to v cc 0.1 1.0 a i ol output leakage v in = 0v to v cc 0.1 1.0 a v il1 (1) input low voltage 2.7v v cc 5.5v ? 0.6 v cc x 0. 3 v ih1 (1) input high voltage v cc x 0.7 v cc + 1 v v ol1 output low voltage 2.7v v cc 5.5v i ol = 2.1 ma 0.4 v v oh1 output high voltage i oh = ? 0.4 ma 2.4 v
4 at93c46 5125a? s eepr? 8 /05 note: 1. this parameter is ensured by characterization only. table 4. ac characteristics applicable over recommended operating range from t a = ? 40c to + 125c, v cc = as s pecified, cl = 1 ttl gate and 100 pf (unless otherwise noted) symbol parameter test condition min typ max units f s k s k clock frequency 4.5v v cc 5.5v 2.7v v cc 5.5v 0 0 2 1 mhz t s kh s k high time 4.5v v cc 5.5v 2.7v v cc 5.5v 250 250 ns t s kl s k low time 4.5v v cc 5.5v 2.7v v cc 5.5v 250 250 ns t c s minimum c s low time 4.5v v cc 5.5v 2.7v v cc 5.5v 250 250 ns t c ss c s s etup time relative to s k 4.5v v cc 5.5v 2.7v v cc 5.5v 50 50 ns t di s di s etup time relative to s k 4.5v v cc 5.5v 2.7v v cc 5.5v 100 100 ns t c s h c s hold time relative to s k0 ns t dih di hold time relative to s k 4.5v v cc 5.5v 2.7v v cc 5.5v 100 100 ns t pd1 output delay to ?1? ac test 4.5v v cc 5.5v 2.7v v cc 5.5v 250 500 ns t pd0 output delay to ?0? ac test 4.5v v cc 5.5v 2.7v v cc 5.5v 250 500 ns t s v c s to s tatus valid ac test 4.5v v cc 5.5v 2.7v v cc 5.5v 250 250 ns t df c s to do in high impedance ac test c s = v il 4.5v v cc 5.5v 2.7v v cc 5.5v 100 100 ns t wp write cycle time 2.7v v cc 5.5v 3 10 ms endurance (1) 5.0v, 25c 1m write cycles
5 at93c46 5125a? s eepr? 8 /05 note: the xs in the address field represent don?t care values and must be clocked. note: 1. this device is not recommended for new designs. please refer to at9 3 c56a. 2. this device is not recommended for new designs. please refer to at9 3 c66a. 3 . the xs in the address field represent don?t care values and must be clocked. table 5. instruction s et for the at9 3 c46 instruction sb op code address data comments x 8 x 16 x 8 x 16 read 1 10 a 6 - a 0 a 5 - a 0 reads data stored in memory, at specified address ewen 1 00 11xxxxx 11xxxx write enable must precede all programming modes era s e111a 6 - a 0 a 5 - a 0 erase memory location a n - a 0 write 1 01 a 6 - a 0 a 5 - a 0 d 7 - d 0 d 15 - d 0 writes memory location a n - a 0 eral 1 00 10xxxxx 10xxxx erases all memory locations. valid only at v cc = 4.5v to 5.5v wral 1 00 01xxxxx 01xxxx d 7 - d 0 d 15 - d 0 writes all memory locations. valid only at v cc = 4.5v to 5.5v ewd s 1 00 00xxxxx 00xxxx disables all programming instructions table 6. instruction s et for the at9 3 c56 (1) and at9 3 c66 (2) instruction sb op code address data comments x 8 x 16 x 8 x 16 read 1 10 a 8 - a 0 a 7 - a 0 reads data stored in memory, at specified address ewen 1 00 11xxxxxxx 11xxxxxx write enable must precede all programming modes era s e111a 8 - a 0 a 7 - a 0 erase memory location a n - a 0 write 1 01 a 8 - a 0 a 7 - a 0 d 7 - d 0 d 15 - d 0 writes memory location a n - a 0 eral 1 00 10xxxxxxx 10xxxxxx erases all memory locations. valid only at v cc = 4.5v to 5.5v wral 1 00 01xxxxxxx 01xxxxxx d 7 - d 0 d 15 - d 0 writes all memory locations. valid only at v cc = 5.0v 10% and disable register cleared ewd s 1 00 00xxxxxxx 00xxxxxx disables all programming instructions
6 at93c46 5125a? s eepr? 8 /05 functional description the at9 3 c46/56/66 is accessed via a simple and versatile 3 -wire serial communication interface. device operation is controlled by seven instructions issued by the host pro- cessor. a valid instruction starts with a rising edge of cs and consists of a s tart bit (logic ?1?) followed by the appropriate op code and the desired memory address location. read (read): the read (read) instruction contains the address code for the mem- ory location to be read. after the instruction and address are decoded, data from the selected memory location is available at the serial output pin do. output data changes are synchronized with the rising edges of serial clock s k. it should be noted that a dummy bit (logic ?0?) precedes the 8 - or 16-bit data output string. erase/write (ewen): to assure data integrity, the part automatically goes into the erase/write disable (ewd s ) state when power is first applied. an erase/write enable (ewen) instruction must be executed first before any programming instructions can be carried out. please note that once in the ewen state, programming remains enabled until an ewd s instruction is executed or v cc power is removed from the part. erase (erase): the erase (era s e) instruction programs all bits in the specified memory location to the logical ?1? state. the self-timed erase cycle starts once the era s e instruction and address are decoded. the do pin outputs the ready/busy sta- tus of the part if c s is brought high after being kept low for a minimum of 250 ns (t c s ). a logic ?1? at pin do indicates that the selected memory location has been erased, and the part is ready for another instruction. write (write): the write (write) instruction contains the 8 or 16 bits of data to be written into the specified memory location. the self-timed programming cycle, t wp , starts after the last bit of data is received at serial data input pin di. the do pin outputs the ready/busy status of the part if c s is brought high after being kept low for a minimum of 250 ns (t c s ). a logic ?0? at do indicates that prog ramming is still in progress. a logic ?1? indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. a ready/busy status cannot be obtained if the cs is brought high after the end of the self- timed programming cycle, t wp . erase all (eral): the erase all (eral) instruction programs every bit in the mem- ory array to the logic ?1? state and is primarily used for testing purposes. the do pin outputs the ready/busy status of the part if c s is brought high after being kept low for a minimum of 250 ns (t c s ). the eral instruction is valid only at v cc = 5.0v 10%. write all (wral) : the write all (wral) instruction programs all memory locations with the data patterns specified in the instruction. the do pin outputs the ready/busy status of the part if c s is brought high after being kept low for a minimum of 250 ns (t c s ). the wral instruction is valid only at v cc = 5.0v 10%. erase/write disable (ewds): to protect against accidental data disturb, the erase/write disable (ewd s ) instruction disables all programming modes and should be executed after all programming operations. the operation of the read instruction is independent of both the ewen and ewd s instructions and can be executed at any time.
7 at93c46 5125a? s eepr? 8 /05 timing diagrams figure 2. s ynchronous data timing note: 1. this is the minimum s k period. notes: 1. this device is not recommended for new designs. please refer to at9 3 c56a. 2. this device is not recommended for new designs. please refer to at9 3 c66a. 3 .a 8 is a don?t care value, but the extra clock is required. 4. a 7 is a don?t care value, but the extra clock is required. figure 3. read timing table 7. organization key for timing diagrams i/o at93c46 (1k) at93c56 (2k) (1) at93c66 (4k) (2) x 8 x 16 x 8 x 16 x 8 x 16 a n a 6 a 5 a 8 ( 3 ) a 7 (4) a 8 a 7 d n d 7 d 15 d 7 d 15 d 7 d 15 high impedance t c s
8 at93c46 5125a? s eepr? 8 /05 figure 4. ewen timing figure 5. ewd s timing figure 6. write timing figure 7. wral timing (1) note: 1. valid only at v cc = 4.5v to 5.5v. c s 11 ... 00 1 s k di t c s c s t c s s k di 1 0 000 ... s k c s t c s t wp 11 a n d n 0a0d0 ... ... di do high impedance bu s y ready c s s k di do high impedance bu s y ready 1 0 0 1 ... d n t c s t wp ... d0 0
9 at93c46 5125a? s eepr? 8 /05 figure 8. era s e timing figure 9. eral timing (1) note: 1. valid only at v cc = 4.5v to 5.5v. s k 1 1 ... 1 c s di a n t c s t s v t df t wp a n-1 a n-2 a0 check s tat u s s tandby ready bu s y do high impedance high impedance s k c s di 1 1 00 0 do high impedance high impedance ready bu s y check s tat u s s tandby t wp t c s t s v t df
10 at93c46 5125a? s eepr? 8 /05 at93c46 ordering information ordering code package operation range at 9 3 c46-10pe-2.7 at 9 3 c46-10 s e-2.7 at 9 3 c46-10te-2.7 8 p 3 8s 1 8 a2 automotive temperature ( ? 40 c to 125 c) at 9 3 c46-10pq-2.7 at 9 3 c46-10 s q-2.7 at 9 3 c46-10tq-2.7 8 p 3 8s 1 8 a2 lead-free/halogen free automotive temperature ( ? 40 c to 125 c) package type 8p3 8 -lead, 0. 3 00" wide, plastic dual inline package (pdip) 8s1 8 -lead, 0.150" wide, plastic gull wing s mall outline (jedec s oic) 8a2 8 -lead, 4.4 mm body, plastic thin s hrink s mall outline package (t ss op) options ? 2.7 low voltage (2.7v to 5.5v)
11 at93c46 5125a? s eepr? 8 /05 packaging information 8p3 ? pdip 2325 orch a rd p a rkw a y s a n jo s e, ca 95131 title drawing no. r rev. 8 p 3 , 8-le a d, 0.300" wide body, pl as tic d ua l in-line p a ck a ge (pdip) 01/09/02 8p3 b note s : 1. thi s dr a wing i s for gener a l inform a tion only; refer to jedec dr a wing ms-001, v a ri a tion ba, for a ddition a l inform a tion. 2. dimen s ion s a a nd l a re me asu red with the p a ck a ge s e a ted in jedec s e a ting pl a ne g au ge gs-3. 3. d, d1 a nd e1 dimen s ion s do not incl u de mold fl as h or protr us ion s . mold fl as h or protr us ion s s h a ll not exceed 0.010 inch. 4. e a nd ea me asu red with the le a d s con s tr a ined to b e perpendic u l a r to d a t u m. 5. pointed or ro u nded le a d tip s a re preferred to e as e in s ertion. 6. b 2 a nd b 3 m a xim u m dimen s ion s do not incl u de d a m ba r protr us ion s . d a m ba r protr us ion s s h a ll not exceed 0.010 (0.25 mm). common dimen s ion s (unit of me asu re = inche s ) s ymbol min nom max note d d1 e e1 e l b 2 b a2 a 1 n ea c b 3 4 plcs a ? ? 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b 2 0.045 0.060 0.070 6 b 3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 ? ? 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2 top view side view end view
12 at93c46 5125a? s eepr? 8 /05 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 10/7/03 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 b common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.00 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? 0? ? 8? ? top view end view side view e b d a a1 n e 1 c e1 l
13 at93c46 5125a? s eepr? 8 /05 8a2 - tssop 2 3 25 orchard parkway s an jose, ca 951 3 1 title drawing no. r rev. 5/ 3 0/02 common dimensions (unit of measure = mm) symbol min nom max note d 2.90 3 .00 3 .10 2, 5 e 6.40 b s c e1 4. 3 0 4.40 4.50 3 , 5 a ? ? 1.20 a2 0. 8 0 1.00 1.05 b 0.19 ? 0. 3 04 e 0.65 b s c l 0.45 0.60 0.75 l1 1.00 ref 8a2 , 8 -lead, 4.4 mm body, plastic thin s hrink s mall outline package (t ss op) notes: 1. this drawing is for general information only. refer to jedec drawing mo-15 3 , variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3 . dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.0 8 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h. 8 a2 b s ide view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indicator this corner e e
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